Optically reconfigurable logic circuit

ABSTRACT

To provide an optically reconfigurable logic circuit in which a mount area of an optical circuit is reduced as much as possible and a high gate density is realized. 
     In an optically reconfigurable logic circuit  1  provided with a plurality of configuration information input circuits  6  for converting an optical signal including logic circuit configuration information into an electric signal and holding and outputting this electric signal and a logic configuration variable circuit  7  for performing logic configuration on the basis of the logic circuit configuration information, the configuration information input circuits  6  holds the logic circuit configuration information as electric charge with use of a junction capacitance and a floating capacitance of a photoconductive device P. An inter-terminal voltage of the photoconductive device P is converted into binary data by a binary circuit and output as a circuit configuration signal. Then, the logic configuration variable circuit  7  is configured to execute a logic arithmetic processing before the inter-terminal voltage of the photoconductive device P drops to be equal to or lower than a logic threshold of the binary circuit due to a leak current.

TECHNICAL FIELD

The present invention relates to an optically reconfigurable logiccircuit capable of performing reconfiguration on an internal circuitlogic configuration while an optical signal that contains logic circuitconfiguration information is input. In particular, the invention relatesto an optically reconfigurable logic circuit capable of increasing agate density of an internal circuit by dynamically holding circuitconfiguration information.

BACKGROUND ART

As a device that can reconfigure a circuit logic configuration whilelogic circuit configuration information is input from the outside, afield programmable gate array: hereinafter referred to as “FPGA” iswidely used. Furthermore, in order to reduce the circuit mount area byincreasing an operating rate of the gate array as much as possible, inrecent years, with the advanced research and development for adynamically reconfigurable device, a demand for a high-speedreconfigurable device is being increased.

However, like the FPGA, with use of a configuration in which a gatearray VLSI and a memory are separated from each other on different chipsand the gate array VLSI and the memory are connected to each other via ametal wiring, it is difficult to realize a device where thereconfiguration can be performed at a high speed. For example, in thecase where the operating frequency of the reconfigurable device is 100MHz and the number of all the reconfiguration bits is 100,000 bits, ifthe reconfigurable device and an external memory are connected to eachother via a single wiring, it is necessary to set the transfer speed to10 Tbps. This transfer speed cannot be realized while the currentstandard CMOS process is used. Even when various revisions are made onthe wiring, the number of usable connection pads in the package islimited to several thousand, and accordingly the speeding up haslimitations. Therefore, it cannot be said that the electricalreconfiguration band the reconfigurable device is sufficiently high withrespect to the reconfiguration bit number.

On the other hand, for example, processors capable performing thereconfiguration at a high speed such as a DAP/DNA (Digital ApplicationProcessor/Distributed Network Architecture) chip and a DRP (dynamicallyreconfigurable processor) are developed (refer to Non-patent Documents11 and 12). Each of them is fabricated by packaging a reconfigurationmemory and a micro processor on one chip. The reconfiguration memoryinside the chip stores a reconfiguration context based on 3 to 16 banks.These banks are switched for each clock. This process is a so-calledcontext switching method. An arithmetic and logic unit (ALU) of thesedevices can perform the reconfiguration for each clock at intervals ofseveral nano seconds. However, these devices have disadvantages of anextreme difficulty of increasing the reconfiguration memory while thegate density is maintained.

In view of the above, to compensate these disadvantages, new devices areproposed and developed by combining various optical and electricalmethods (refer to Non-patent Documents 7 to 10). Among those devices inparticular, an optically reconfigurable gate array: hereinafter referredto as “ORGA” (refer to Patent Documents 1 and 2 and Non-patent Documents1 to 3, and 6) and an optically differential reconfigurable gate array:hereinafter referred to as “ODRGA” (refer to Patent Document 3 andNon-patent Documents 4 and 5) are known which can shorten thereconfiguration time of the conventional FPGA. These devices are similarto the FPGA, but have a difference from the FPGA in that thereconfiguration on the gate array logic configuration is performed withuse of optical signal input from an external optical memory.Hereinafter, similar to the ORGA and the ODRGA, devices that can performthe reconfiguration on the logic circuit with use of the optical signalinput are generally referred to as “optically reconfigurable logiccircuit”.

FIG. 18 shows a configuration of an optically reconfigurable logiccircuit. An optically reconfigurable logic circuit 100 is composed of anoptical part 101 and a VLSI area 102. The optical part 101 is providedwith an optical system for irradiating the VLSI area 102 with an opticalsignal that contains logic circuit configuration information (refer toPatent Documents 1 to 5 and Non-patent Documents 1 to 5).

The optical part 101 is composed of an optical memory element such as aholographic memory or a spatial light modulator that stores the logiccircuit configuration information and a light emitting element such as alaser or an LED for outputting irradiation light for reading the logiccircuit configuration information from the optical memory element (referto Patent Documents 2, 4, and 5 and Non-patent Document 2). With use ofthe light output from the light emitting element, the logic circuitconfiguration information is read out as an optical signal from theoptical memory element.

Mounted to the VLSI area 102 are a configuration information inputcircuit provided with a light receiving element for detecting an opticalsignal input from the optical part 101, a logic configuration variablecircuit for performing configuration on a logic structure on the basison the logic circuit configuration information given by the opticalsignal input to the configuration input information input circuit, aninput/output circuit for performing input and output of an externalsignal with respect to a logic configuration variable circuit, acontroller for performing a control on the operation of the opticallyreconfigurable logic circuit 100 as a whole, and the like are mounted(refer to Patent Documents 1 to 3 and 5).

FIG. 19 shows an example of a configuration information input circuit ina conventional optically reconfigurable logic circuit (refer to PatentDocument 3). FIG. 19 illustrates a configuration information inputcircuit used in an ODRGA.

This configuration information input circuit denoted by referencenumeral 105 is provided with a photo diode D, a PMOS transistor M, and aT flip-flop (triggered flip-flop: hereinafter referred to as “TFF”). Thephoto diode D is subjected to reverse direction connection, and an anodeis grounded. A cathode of the photo diode D is connected to a powersource via the PMOS transistor M. The preset signal nPRESET is input tothe gate of the PMOS transistor M (herein, symbol “n” represents anegative logic. In the drawings, the negative logic is indicated by anoverline. The same holds true in the following description). The nPRESETis a negative logic, and when the nPRESET is 0, the cathode of the photodiode D is applied with a power source voltage Vc.

A common node N1 for the photo diode D and the PMOS transistor M isconnected to a trigger input terminal nT of the TFF. A clock signal(CLOCK) is input to a clock terminal of the TFF, and a clear signal(nCLEAR) is input to a clear terminal nCLR of the TFF. The CLEAR is anegative logic signal. A 1-bit circuit configuration signal (CONFIG) isoutput from the output terminal Q of the TFF. The circuit configurationsignal is a signal representing the logic circuit configurationinformation of the logic configuration variable circuit.

At the initial rise of CLOCK, when the input of the trigger inputterminal nT is 1, the TFF reverses the logic value of the CONFIG, andwhen the input of the trigger input terminal nT is 0, the TFF keeps thelogic value of the CONFIG. In addition, when the nCLEAR is 0, the TFFforcedly sets the CONFIG as 0.

A description will be given to the case in which the reconfiguration isperformed on the logic configuration variable circuit.

(1) First of all, the nPRESET is set as 0, and after the power sourcevoltage Vc is applied between the terminals of the photo diode D, thenPRESET is set as 1. As a result, due to a reversed bias junctioncapacitor of the photo diode D, the node N1 is set at an H level.

(2) Next, an optical signal is input from the optical part 101. Herein,when the photo diode D is irradiated with light, a current flows throughthe photo diode D. Therefore, a potential of the node N1 is set at an Llevel. When the photo diode D is not irradiated with light, the node N1is kept at the H level.

(3) After the input of the optical signal from the optical part 101 iscompleted, at the initial rise of the CLOCK, when the node N1 is at theL level, the value of the CONFIG is kept, and when the node N1 is at theH level, the value of the CONFIG is reversed. As a result, the logicconfiguration switching of the logic configuration variable circuit isperformed.

The above-mentioned operations (1) to (3) are hereinafter referred to as“refresh”.

The above-mentioned configuration is an example of a configurationinformation input circuit used in the ODRGA. When the configuration isused for the ORGA, instead of the TFF in FIG. 19, a D flip-flop, alatch, a memory, or the like is used.

[Patent Document 1]

Japanese Unexamined Patent Application Publication No. [Patent Document2]

U.S. Pat. No. 6,057,703

[Patent Document 3]

Japanese Unexamined Patent Application Publication No. 2004-064017

[Patent Document 4]

U.S. Pat. No. 6,222,755

[Patent Document 5]

U.S. Pat. No. 6,072,608

[Non-patent Document 1]

J. V. Campenhout, H. V. Marck, J. Depreitere, and J. Dambre,“Optoelectronic FPGA's”, IEEE J. Sel. Top. Quantum Electronics, Vol. 5,pp. 306-315, 1999.

[Non-patent Document 2]

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna,and E. R. Fossum, “Optically Programmable Gate Array”, Proc. SPIE—Int.Soc. Opt. Eng., Vol. 4089, pp. 763-771, 2000.

[Non-patent Document 3]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D.Psaltis, “Optical memory for computing and information processing”,Proc. SPIE—Int. Soc. Opt. Eng., Vol. 3804, pp. 14-24, 1999.

[Non-patent Document 4]

M. Watanabe, F. Kobayashi, “An optically differential reconfigurablegate array and its power consumption estimation”, IEEE InternationalConference on Field-Programmable Technology, pp. 197-202, 2002.

[Non-patent Document 5]

M. Watanabe, F. Kobayashi, “An Optically Differential ReconfigurableGate Array with a dynamic reconfiguration circuit”, 10th ReconfigurableArchitectures Workshop, p. 188, 2003.

[Non-patent Document 6]

J. Depreitere, H. Neefs, H. V. Marck, J. V. Campenhout, R. Baets, B.Dhoedt, H. Thienpont, and I. Veretennicoff, “An optoelectronic 3-D fieldprogrammable gate array”, FPL '94. Proc., pp. 352-360, 1994.

[Non-patent Document 7]

Ted H. Szymanski, Martin Saint-Laurent, Victor Tyan, Albert Au, andBoonchuay Supmonchai, “Field-programmable logic devices with opticalinput-output”, Applied Optics, vol. 39, Issue 5, pp. 721-732, February2000.

[Non-patent Document 8]

Sherif S. Sherif, Stefan K. Griebel, Albert Au, Dennis Hui, Ted H.Szymanski, and H. Scott Hinton, “Field-programmable smart-pixel arrays:design, VLSI implementation, and applications”, Applied Optics, Volume38, Issue 5, pp. 838-846, February 1999.

[Non-patent Document 9]

Majd F. Sakr, Steven P. Levitan, C. Lee Giles, and Donald M. Chiarulli,“Reconfigurable processor employing optical channels”, Proceedings ofthe 1998 International Topical Meeting on Optics in Computing (OC'98),Proceedings of the SPIE, Vol. 3490, pp. 564-567, 1998.

[Non-patent Document 10]

M. Watanabe, J. Ohtsubo, “Digital associative memory neural network withoptical learning capability”, Optics Communications, Vol. 113, pp.31-38, 1994.

[Non-patent Document 11]

Hirotaka Nakano, Takeshi Shindo, Tetsuo Kazami, and Masato Motomura,“Development of Dynamically Reconfigurable Processor LSI”, NEC TECHNICALJOURNAL, NEC Corporation, April 2003, Vol. 56, No. 4, pp. 99-102.

[Non-patent Document 12]

U. Tangen, J. S. McCaskill, “Hardware evolution with a massivelyparallel dynamically reconfigurable computer: POLYP”, Evolvable Systems:From Biology to Hardware. Second International Conference, ICES 98Proc., pp. 364-371, 1998.

DISCLOSURE OF INVENTION Problems to be Solved by the Invention

According to the conventional optically reconfigurable logic circuit,reconfiguration means for a logic configuration with use of opticalinput is adopted. For that reason, the VLSI area 102 of the conventionaloptically reconfigurable logic circuit includes, similarly to the normalFPGA, the logic configuration variable circuit and a large number ofconfiguration information input circuits. In other words, it can beconsidered that the conventional ORGA or ODRGA is fabricated by addingan optical circuit on a gate array of the FPGA.

The respective configuration information input circuits need a photodiode for detecting the optical logic circuit configuration information,a latch, a flip-flop, or a memory for temporarily storing the logiccircuit configuration information, and some transistors.

However, for example, when the mount size of the photo diode in the 0.35μm process is 25 μm² and the number of gates is 65 kG, the occupyingratio of the optical circuit in the VLSI chip mount area of the ODRGA isestimated to reach as high as about 47%. In this way, if the occupyingratio of the optical circuit with respect to the mount area is high, ahigh gate density ORGA or ODRGA cannot be realized.

On the other hand, in the above-mentioned conventional configuration,both sides of the optical part 101 and the VLSI area 102 have a memoryfunction. Therefore, it can be considered that the conventionaloptically reconfigurable logic circuit has the memory functionredundantly as a whole.

The memory function of the VLSI area 102 has an important function ofholding the output values of the configuration information inputcircuits while the photo diodes are refreshed. However, if the memoryfunction of the VLSI area 102 could be eliminated, the mount area of theconfiguration information input circuits is significantly reduced. As aresult, it is considerable that the gate density of the opticallyreconfigurable logic circuit could be extremely increased.

In view of the above, an object of the present invention is to providean optically reconfigurable logic circuit capable of reducing an mountarea of an optical circuit as much as possible and realizing a high gatedensity.

Means for Solving the Problems

According to a first aspect of the present invention, an opticallyreconfigurable logic circuit includes: a configuration information inputcircuit that includes a photoconductive device for causingcontinuity/interruption in response to light irradiation input, andconverts and outputs an optical signal that contains logic circuitconfiguration information with use of the photoconductive device into anelectric circuit configuration signal; and a logic configurationvariable circuit for performing logic configuration of an internalcircuit on the basis of the circuit configuration signal, the opticallyreconfigurable logic circuit being characterized in that a control isperformed in such a manner that the logic circuit configurationinformation input from the optical signal is held at a parasiticcapacitance (hereinafter referred to as “input capacitor”) between theterminals of the photoconductive device in a non-continuity state as thecircuit configuration signal, and as the input capacitor is preset and anext optical signal is input before the held circuit configurationsignal disappears due to leak discharge, the logic circuit configurationinformation is dynamically held at the input capacitor.

According to this configuration, in the case where the writing of thelogic circuit configuration information is performed, while the electriccharge is charged to the input capacitor structured by the parasiticcapacitance of the photoconductive device (which is formed of a junctioncapacitance of the photoconductive device and other floatingcapacitance), the optical signal that contains the logic circuitconfiguration information is input to the optically reconfigurable logiccircuit.

At this time, the photoconductive device to which no optical signal isinput is kept at the state in which the electric charge of the inputcapacitor is held. On the other hand, the photoconductive device towhich the optical signal is input discharges the electric charge of theinput capacitor as the carrier occurs in the depletion layer. As aresult, the logic circuit configuration information of the opticalsignal is converted into the electric charge amount (that is, theinter-terminal voltage of the photoconductive device). Then, after theinput of the optical signal, the logic circuit configuration informationis held at the input capacitor of the photoconductive device as theelectric charge amount (that is, the inter-terminal voltage of thephotoconductive device). The inter-terminal voltage of thephotoconductive device is output as the circuit configuration signal.

On the basis of the circuit configuration signal, the logicreconfiguration on the logic configuration variable circuit isperformed. In general, the input stage of the logic configurationvariable circuit has high input impedance, and thus the drop of theinter-terminal voltage of the photoconductive device during a period inwhich the optical signal is not input is hardly occurred except in thecase of the voltage drop due to the leak current. Therefore, the circuitconfiguration signal is kept stable over a relatively long period oftime. The logic configuration variable circuit performs the targetedlogic operation processing with use of the logic circuit configured onthe basis of the circuit configuration signal while the output value ofthe configuration information input circuit is not changed.

In this way, according to this configuration, in the configurationinformation input circuit, without additionally providing a memorycircuit such as a latch, a flip-flop, or a memory for holding the logiccircuit configuration information, with use of the input capacity formedof the junction capacitance and the floating capacitance of thephotoconductive device, the logic circuit configuration information ishold. As a result, excess memory functions are eliminated, the mountarea and the electricity consumption of the configuration informationinput circuit is significantly reduced as compared with the prior art.

Then, before the circuit configuration information held at the inputcapacitor disappears due to the leak discharge, the input capacitor ispreset and refreshed by the next input of the optical signal. For thatreason, the circuit configuration information of the input capacitor cankeep being dynamically held continuously.

Herein, for “the photoconductive device”, a photo diode, a phototransistor, a photoconductive cell, or the like can be used. It shouldbe noted that “the logic circuit configuration information isdynamically held” means keeping the state in which the logic circuitconfiguration information is periodically refreshed, thereby holding thelogic circuit configuration information.

According to a second aspect of the present invention, in the firstaspect, the optically reconfigurable logic circuit is characterized inthat the photoconductive device is a photo diode subjected to reversebias connection.

According to this configuration, the photo diode is used as thephotoconductive device and the mount area can be further reduced,whereby the optically reconfigurable logic circuit can be set to havehigh gate number as much as possible.

Herein, for “the photo diode”, a PN photo diode, a PIN photo diode, aSchottky photo diode, an Avalanche photo diode or the like can be use.In particular, it is effective to use the PN photo diode for simplifyingthe manufacturing process and reducing the mount area.

According to a third aspect of the present invention, in the first orsecond aspect, the optically reconfigurable logic circuit ischaracterized in that the configuration information input circuitincludes a logic output circuit for quantizing an inter-terminal voltageof the photoconductive device and outputting the resultant as a logicoutput value, and the logic output circuit quantizes an electric signalwhich is output when the photoconductive device converts the opticalsignal, and outputs the resultant as the circuit configuration signal.

According to this configuration, the output of the photoconductivedevice is quantified with use of the logic output circuit, whereby it ispossible to output the stable signal as the circuit configurationsignal.

Herein, for “the logic output circuit”, a CMIS (Complementary MetalInsulator Semiconductor) inverter circuit, a comparison circuit, or thelike can be used. In view of making the mount area small, use of theCMIS inverter circuit is preferable.

According to a fourth aspect of the present invention, in any one of thefirst to third aspects, the optically reconfigurable logic circuit ischaracterized by further including preset control means for performing apreset control for charging the input capacitor by applying thephotoconductive device with a preset voltage in a reverse biasdirection; irradiation light control means for performing irradiationcontrol for writing logic circuit configuration information to theconfiguration information input circuit by setting the optical signal inan on state in a predetermined period of time and causing continuity ofthe irradiated photoconductive device on the basis of the optical signalafter the input capacitor is charged through the preset control; andtiming generation means for outputting a preset timing signal to thepreset control means with a predetermined delay time after the logiccircuit configuration information is written to the configurationinformation input circuit through the irradiation light control, theoptically reconfigurable logic circuit characterized in that the presetcontrol means executes the preset control when the preset timing signalis input.

According to this configuration, in the case where the logic circuitconfiguration information held by the configuration information inputcircuit is updated, first of all, the preset control means applies thepreset voltage between the electrodes of the photoconductive device inthe reverse bias. As a result, the input capacitor formed of theparasitic capacitance of the photoconductive device is charged with theelectric charge. Next, the preset control means stops the application ofthe preset voltage. Then, the light irradiation control means performssuch a control that the optical signal that contains the logic circuitconfiguration information is input to the optically reconfigurable logiccircuit. As a result, the update of the logic circuit configurationinformation held at the configuration information input circuit can beconducted. It should be noted that the series of the logic circuitconfiguration information update operations is referred to as “refresh”.

As described above, the drop of the inter-terminal voltage of thephotoconductive device during a period in which the optical signal isnot input hardly occurs expect in the case of the voltage drop due tothe leak current. Therefore, the circuit configuration signal can bekept stable over a relatively long period. The preset control means andthe light irradiation control means performs the refresh before thevoltage between terminals of the input capacitor falls to be equal to orlower than the logic threshold of the logic output circuit due to theleak current, and therefore the logic circuit configuration informationis continuously held at the configuration information input circuit. Thelogic configuration variable circuit performs the targeted logicoperation processing during a period from the update of the logiccircuit configuration information to the update of the next logiccircuit configuration information.

In this way, according to this configuration, by dynamically updatingthe logic circuit configuration information of the configurationinformation input circuit with use of the preset control means and thelight irradiation control means, it is possible to prevent such asituation that the logic configuration of the logic configurationvariable circuit becomes undetermined unexpectedly due to thedisappearance of the logic circuit configuration information due to theleak discharge.

Herein, “the predetermined delay time” in which the timing generationmeans outputs the preset timing signal is appropriately set to a timeshorter than the time interval after the input of the optical signalbefore the disappearance of the circuit configuration information of theinput capacitor due to the leak discharge.

According to a fifth aspect of the present invention, in the fourthaspect, the optically reconfigurable logic circuit is characterized inthat the timing generation means outputs a preset timing signal to thepreset control means with a delay time shorter than a period in whichthe inter-terminal voltage of the photoconductive device that ispreviously set to the preset voltage through the preset control falls tobe equal or lower than a predetermined logic threshold due to the leakdischarge.

In this way, during a period after the preset before the drop of theinter-terminal voltage of the photoconductive device to be equal to orlower than the predetermined logic threshold, as the timing generationmeans outputs the preset signal to the preset control means again, theupdate of the circuit configuration information of the input capacitoris executed. As a result, the circuit configuration information of theinput capacitor can be dynamically held.

Herein, “the predetermined logic threshold” is a logic threshold voltagedetermined by a semiconductor circuit structuring the opticallyreconfigurable logic circuit.

According to a sixth aspect of the present invention, in the fourth orfifth aspect, the optically reconfigurable logic circuit ischaracterized in that the configuration information input circuitincludes a preset switching element for performing turning on/off of thepreset voltage applied between electrodes of the photoconductive device,and the preset control means asserts in a predetermined period thepreset signal for turning on the preset switching element.

According to this configuration, while the preset switching element isturned on in response to the preset signal, the application of thepreset voltage is applied between the electrodes of the photoconductivedevice, and the input capacitor is preset. After that, the input signalis irradiated and input to the photoconductive device, thereby making itpossible to write the circuit configuration information to the inputcapacitor.

Herein, for “the preset switching element”, a switching element such asa MISFET (Metal Insulator Semiconductor Field Effect Transistor) or abipolar transistor can be used. In addition, the preset switchingelement can be connected to the anode or the cathode with respect to thephotoconductive device. In addition, “the predetermined period” forasserting the preset signal is to a sufficient period of time in whichthe voltage of the input capacitor saturates to the preset voltage.

According to a seventh aspect of the present invention, in any one ofthe third to fifth aspects, the optically reconfigurable logic circuitis characterized by further including logic output holding means forholding a logic output value of the logic configuration variable circuitat a timing before a time point when the inter-terminal voltage of thephotoconductive device falls to be equal to or lower than thepredetermined logic threshold as the input capacitor charged to thepreset voltage through the preset control involves leak discharge.

According to this configuration, during the period of the logic circuitconfiguration information of the configuration information inputcircuit, the output signal of the logic configuration variable circuitis temporarily held by the external output memory means. Therefore, evenwhen the logic structure of the internal circuit of the logicconfiguration variable circuit becomes undetermined during the update ofthe logic circuit configuration information, it is possible to preventthe situation in which the logic output value of the logic configurationvariable circuit becomes undetermined.

In the case of additionally providing the logic output holding means,the additional mount area is accordingly necessary. However, in general,all the logic circuit configuration information of the logicconfiguration variable circuit is significantly lower than the number ofall the bits. Therefore, as compared with the conventional case in whichmemory elements are mounted corresponding to all the photoconductivedevices, the mount area can be considerably reduced.

Herein, for “the logic output holding means”, a memory element that isusually used such as a latch, a flip-flop, or a register can be used.

According to an eighth aspect of the present invention, in the seventhaspect, the optically reconfigurable logic circuit is characterized inthat the configuration information input circuit includes a presetswitching element for performing turning on/off of a preset voltage thatis applied between the electrodes of the photoconductive device, thepreset control means asserts in a predetermined period the preset signalfor turning on the preset switching element, and the logic outputholding means holds the logic output value of the logic configurationvariable circuit at a timing before the preset control means asserts thepreset signal.

According to this configuration, as the logic output holding means holdsthe logic output value of the logic configuration variable circuitbefore the input capacitor is preset by the preset after the circuitconfiguration information is held at the input capacitor, while thecircuit configuration information of the input capacitor is updated, theprevious circuit configuration information is held and the logicconfiguration of the logic configuration variable circuit is maintained.Therefore, the logic structure of the internal circuit of the logicconfiguration variable circuit becomes undetermined while the logiccircuit configuration information is updated, and it is possible toprevent the situation in which the logic output value of the logicconfiguration variable circuit becomes undetermined.

According to a ninth aspect of the present invention, in any one offourth to sixth aspects, the optically reconfigurable logic circuit ischaracterized by further including a pass transistor for causingcontinuity/interruption of a circuit configuration signal transmissionline for inputting the circuit configuration signal, which is outputfrom the configuration information input circuit, to the logicconfiguration variable circuit; and pass transistor control means forperforming such a control that the circuit configuration signal is heldat one of the circuit configuration signal transmission line and aparasitic capacitance (hereinafter referred to as “output capacitor”) ofan input circuit of the logic configuration variable circuit to whichthe circuit configuration signal transmission line is connected as thepass transistor is set in the interruption state during the irradiationof the optical signal.

According to this configuration, during a period in which the update ofthe circuit configuration information of the input capacitor isconducted in response to the preset and the irradiation of the opticalsignal (hereinafter referred to as “refresh period”), by holding thecircuit configuration signal at the output capacitor, even during therefresh period, the logic configuration of the logic configurationvariable circuit is kept and the execution can be performed.

Also, the parasitic capacitance of the circuit configuration signaltransmission line or the input circuit of the logic configurationvariable circuit to which the circuit configuration signal transmissionline is connected is used for the output capacitor, and thus an elementadded to the configuration information input circuit is only a passtransistor, thereby achieving the small mount area and high gate number.

According to a tenth aspect of the present invention, in the eighthaspect, the optically reconfigurable logic circuit is characterized inthat the pass transistor control means performs such a control that,after irradiation of the optical signal, as the input capacitor chargedto the preset voltage through the preset control involves leakdischarge, before a time point when the inter-terminal voltage of thephotoconductive device falls to be equal or lower than the predeterminedlogic threshold, at least during a period in which logic reconfigurationon the logic configuration variable circuit is completed, the passtransistor is set in the continuity state, and during the irradiation ofthe optical signal, the pass transistor is set in the interrupted state.

As a result, the logic configuration of the logic configuration variablecircuit is guarantied with certainty on the basis of the circuitconfiguration information held at the input capacitor.

According to an eleventh aspect of the present invention, in any one offourth to tenth aspects, the optically reconfigurable logic circuitfurther includes the optical signal input means for irradiating theconfiguration information input circuit with the optical signal thatcontains the logic circuit configuration information, and ischaracterized in that the light irradiation control means controlsturning on/off for the selection and irradiation of the optical signaloutput from the optical signal input means.

According to this configuration, the optical signal input means performsthe operation for repeating the update of the logic circuitconfiguration information while performing the selection of the opticalsignal, and can realize the optically reconfigurable logic circuit inwhich the logical configuration is dynamically changed.

According to a twelfth aspect of the present invention, in the eleventhaspect, the optically reconfigurable logic circuit is characterized inthat at least two of the logic configuration variable circuits areconnected in parallel to each other with a common input/output terminalfor a logic variable, the optical signal input means can independentlyinput an optical signal that contains the logic circuit configurationinformation to the configuration information input circuitscorresponding to the respective logic configuration variable circuit,and the optical signal input means includes open collector circuitsprovided at output stages of the logic configuration variable circuitsand reconfiguration control means for performing such a control on theoptical signal input means that switching is performed among the logicconfiguration variable circuits connected in parallel to each other sothat at the same time point, the configuration information input circuitcorresponding to at least one of the logic configuration variablecircuits is not irradiated with the optical signal and optical signalsthat contain the same logic circuit configuration information are inputto the logic configuration variable circuits.

According to this configuration, reconfiguration can be conducted forthe respective logic configuration variable circuits. Therefore, each ofthe logic configuration variable circuits connected in parallel has theidentical circuit configuration. Then, when reconfiguration is conductedon the logic configuration variable circuits, among the logicconfiguration variable circuits connected in parallel, while at leastone of the logic circuit configurations is kept, reconfiguration isconducted on the other logic configuration variable circuits. At thistime, the output stages of the respective logic configuration variablecircuits are open collector circuits, and thus the output value of thelogic configuration variable circuit in which the logic circuitconfiguration is kept is output to the output terminal. Therefore, whilethe logic circuit inside the logic configuration variable circuit isreconfigured, it is possible to prevent such a situation that the outputvalue of the logic configuration variable circuit becomes undetermined.

According to the sixth aspect of the present invention, in any one ofthe first to fifth aspects, the optically reconfigurable logic circuitis characterized in that the photoconductive device is the photo diodein the reverse bias, and the configuration information input circuitholds the logic circuit configuration information as electric chargewith use of the input capacitor formed of the junction capacitance andthe floating capacitance of the photo diode.

According to this configuration, as the photo diode is used for thephotoconductive device, the mount area of the photoconductive device isparticularly made small, and the mount area of the configurationinformation input circuit can be reduced.

EFFECT OF THE INVENTION

As described above, according to the present invention, in theconfiguration information input circuit, such a configuration is adoptedthat the logic circuit configuration information is held with use of theinput capacitor formed of the junction capacitance and the floatingcapacitance of the photoconductive device, the mount area and powerconsumption of the configuration information input circuit can besignificantly reduced as compared with the prior art. As a result, themount area of the optical circuit is reduced, and it is possible torealize the high gate density.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 A block diagram of a function configuration of an entirety of anoptically reconfigurable logic circuit according to a first embodimentof the present invention.

FIG. 2 A circuit diagram of a configuration example of a logicconfiguration variable circuit.

FIG. 3 A diagram of a configuration example of the logic block in FIG.2.

FIG. 4 A diagram of a configuration example of the switching matrix inFIG. 2.

FIG. 5 A circuit diagram of a configuration example of the informationinput circuit.

FIG. 6 A timing drawing of operations of the configuration informationinput circuit.

FIG. 7 A diagram of a configuration of an output holding circuit.

FIG. 8 A timing drawing for describing operations of the output holdingcircuit.

FIG. 9 A diagram of another configuration of the output holding circuit.

FIG. 10 A block diagram of an entire function configuration of anoptically reconfigurable logic circuit according to a second embodimentof the present invention.

FIG. 11 A diagram of a configuration of an output circuit.

FIG. 12 A block diagram of an entire function configuration of anoptically reconfigurable logic circuit according to a third embodiment.

FIG. 13 A diagram for displaying the configuration information inputcircuit at transistor level. FIG. 13 (a) is for the configurationinformation input circuit in FIG. 5( a), and FIG. 13 (b) is for theconfiguration information input circuit according to the thirdembodiment.

FIG. 14 A timing chart for the reconfiguration operations on theoptically reconfigurable logic circuit according to the first embodimentand the execution of the logic configuration variable circuit.

FIG. 15 A timing chart for the reconfiguration operations on theoptically reconfigurable logic circuit according to the third embodimentand the execution of the logic configuration variable circuit.

FIG. 16 A circuit diagram of a dynamic optically reconfiguration arrayfor performing partial reconfiguration according to the thirdembodiment.

FIG. 17 A timing chart of an operation schedule for dynamicreconfiguration operations of the dynamic optically reconfigurationarray in FIG. 16 and the execution of the logic configuration variablecircuit.

FIG. 18 A diagram of a configuration of the optically reconfigurablelogic circuit.

FIG. 19 A diagram of an example of the configuration information inputcircuit in a conventional optically reconfigurable logic circuit.

REFERENCE NUMERALS

-   1, 1′ optically reconfigurable logic circuit-   2 optical section-   3 VLSI section-   4 optical memory-   5 light irradiation section-   6, 6 b configuration information input circuit-   6 a optical reconfiguration instruction circuit-   7, 7′, 7 a, 7 b logic configuration variable circuit-   8, 9 input/output circuit-   10 output holding circuit-   11 preset control section-   12 irradiation light control section-   13 timer-   14 I/O block-   15 logic block-   16 switching matrix-   16 a connection switching circuit-   16 b analog switch-   17 connection wiring-   18 input variant selection circuit-   19 lookup table-   19 a multiplexer-   20 D flip-flop (DFF)-   21 output variant selection circuit-   22 output wiring selection circuit-   22 a tristate buffer-   23 clear signal selection circuit-   25 D flip-flop (DFF)-   26 transmission gate-   27 latch-   30 output circuit-   31 open collector circuit-   40 pass transistor control section-   41 input buffer-   42 circuit configuration signal transmission line-   43 logic output circuit with pass transistor-   P photo diode-   M preset switching element-   M2 pass transistor-   DIG logic output circuit-   C input capacitor-   C′ output capacitor

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a description will be given to a best mode for implementingthe present invention with reference to the drawings.

First Embodiment

FIG. 1 is a block diagram of a function configuration of an entirety ofan optically reconfigurable logic circuit according to a firstembodiment of the present invention. An optically reconfigurable logiccircuit 1 is provided with an optical section 2 (optical signal inputmeans) and a VLSI section 3. The optical section 2 is a section foroutput logic circuit configuration information as an optical signal. TheVLSI section 3 is a section for constructing a logic configuration of aninternal circuit and performing an arithmetic processing on the basis ofthe logic circuit configuration information that is contained in theoptical signal input from the optical section 2.

The optical section 2 is provided with an optical memory 4 and a lightirradiation section 5. The optical memory 4 is a memory for opticallystoring the logic circuit configuration information. The lightirradiation section 5 is provided with a light emitting element foremitting light for reading out the logic circuit configurationinformation stored in the optical memory 4. The light emitted from lightirradiation section 5 (hereinafter referred to as “the reference light”)functions as an optical signal that is pattern light that is irradiatedthrough the optical memory 4 and includes the logic circuitconfiguration information. The VLSI section 3 is irradiated with thisoptical signal.

For the optical memory 4, a hologram memory, a spatial light modulator(a liquid spatial light modulator or the like) etc. are used. For thelight irradiation section 5, a semiconductor laser array and the likeare used. By changing the angle of the reference light emitted from thelight irradiation section 5 to the optical memory 4 or speciallychanging of an optical modulation characteristic the optical memory 4,the logic circuit configuration information read out from the opticalmemory 4 is switched.

It should be noted that with regard to the optical section 2, varioussimilar members described in Patent Documents 2, 4, and 5, etc. areknown up to now, so a detailed description will be omitted here.

The VLSI section 3 includes a plurality of configuration informationinput circuits 6, a logic configuration variable circuit 7, input/outputcircuits 8 and 9, an output holding circuit 10, a preset control section11, an irradiation light control section 12, and a timer 13. These partsare mounted on one VLSI chip.

The configuration information input circuit 6 is provided with a photodiode P that is one type of a photoconductive device. As will bedescribed later, the photo diode P is subjected to reverse directionconnection and functions as a capacitor (hereinafter referred to as“input capacitor”) C formed of a parasitic capacitance (the junctioncapacitance and the floating capacitance). The configuration informationinput circuit 6 is adapted to convert the optical signal emitted fromthe optical section 2 into an electric signal with use of the photodiode P. In addition, configuration information input circuit 6temporarily holds the electric signal that contains the logic circuitconfiguration information and outputs the signal as a voltage signal. Atthis time, the logic circuit configuration information is held in theinput capacitor C of the photo diode P as the electric charge amount.Then, with use of a logic output circuit DIG at the high input impedance(refer to FIG. 5), the inter-terminal voltage of the photo diode P isconverted into binary data and output.

The logic configuration variable circuit 7 performs the internal logiccircuit configuration on the basis of the logic circuit configurationinformation output from the respective configuration information inputcircuits 6. Then, with the thus configured logic circuit, the logicconfiguration variable circuit 7 executes a logic arithmetic processing.

It should be noted that in FIG. 1, for the convenience for describingthe functional configuration, the respective configuration informationinput circuits 6 and the logic configuration variable circuit 7 areseparated from each other for description, but physically, as will bedescribed later, the respective configuration information input circuits6 are dispersed and incorporated at parts of the logic configurationvariable circuit 7.

The input/output circuits 8 and 9 are interfaces for controlling theinput of the logic variable from the external circuit to the VLSIsection 3 and the output of the logic variable from the VLSI section 3to the external circuit.

The output holding circuit 10 is a circuit for temporally holding theoutput of the logic configuration variable circuit 7 while thereconfiguration of the logic of the logic configuration variable circuit7.

The preset control section 11 irregularly and intermittently outputs thepreset signal nPRESET for performing the preset on the respectiveconfiguration information input circuits 6. It should be noted that thetime interval in which the preset control section 11 outputs the presetsignal nPRESET is set to a shorter time in which at least the electriccharge charged to the input capacitor C of the photo diode P dischargesdue to the leak current (leak discharge) and the inter-terminal voltageof the photo diode P becomes equal to or lower than the logic thresholdof the logic output circuit DIG. The time for outputting the presetsignal nPRESET is set to about a saturation time of the input capacitorC of the photo diode P of the respective configuration information inputcircuits 6. These times are measured by the timer 13 (timing generationmeans). In other words, the timer 13 measures the time for performingthe preset and periodically outputs the preset timing signal to thepreset control section 11. The preset control section 11 outputs thepreset signal nPRESET on the basis of this preset timing signal.

Usually, the attenuation time in which the inter-signal voltage of thephoto diode P reduces due to the leak discharge is set to a long time ofabout several tens milliseconds. Therefore, the time interval in whichthe preset control section 11 outputs the preset signal nPRESET can beset to a sufficiently long time interval as compared with the time inwhich the logic configuration variable circuit 7 performs the logicarithmetic processing on one task.

After the preset control section 11 completes outputting the presetsignal nPRESET, the irradiation light control section 12 performs thecontrol on the optical section 2 such that the light irradiation section5 of the optical section 2 outputs the optical signal only for apredetermined time.

FIG. 2 is a circuit diagram of an example of the logic configurationvariable circuit 7A. The logic configuration variable circuit 7 includesthe general FPGA except the input area of the logic circuitconfiguration information. The logic configuration variable circuit 7includes four I/O blocks 14, four logic blocks 15, five switchingmatrices 16, and connection wirings 17. At parts inside the respectivelogic blocks 15 and the respective switching matrices 16, theconfiguration information input circuits 6 are incorporated.

The four I/O blocks 14 are circuits for distributing to connectionwirings 17 the input variants with respect to the logic configurationvariable circuit 7 and performing the signal distribution for outputtingthe output variants of the logic configuration variable circuit 7 to theexternal output lines.

The four logic blocks 15 are located at apexes of the respectiverectangles. The logic blocks 15 is a logic arithmetic processing circuitfor performing the configuration on the logic structure on the basis ofthe logic circuit configuration information output from theconfiguration information input circuits 6.

The respective switching matrices 16 are located at midpoints of foursides of a rectangle surrounding the four logic blocks 15 and the centerof the rectangle. In addition, among the respective switching matrices16, among the respective switching matrices 16 and the respective logicblocks 15, and among the respective logic blocks 15, connections areachieved by a plurality of connection wirings 17. The switching matrices16 are switching circuits for performing the switching on the connectiondirection of the connection wirings 17 on the basis of the logic circuitconfiguration information output from the configuration informationinput circuits 6.

Moreover, the four I/O blocks 14 are provided corresponding to the fourswitching matrices 16 located at located at midpoints of four sides of arectangle surrounding the four logic blocks 15. The four switchingmatrices 16 are connected to the corresponding I/O blocks 14 via theplurality of connection wirings 17. Then, via the I/O blocks 14 performsthe input and output of the logic variable with respect to the externalcircuit.

FIG. 3 is a diagram of an example of a configuration the logic block 15in FIG. 2. The logic block 15 shown in this example includes four inputvariant selection circuits 18, a lookup table 19, a D flip-flop(hereinafter referred to as “DFF”) 20, an output variant selectioncircuit 21, eight output wiring selection circuits 22, and a clearsignal selection circuit 23.

The respective input variant selection circuits 18 is composed of fiveinput lines which are different from each other and connected to theconnection wirings 17, two input lines to which logic 0 and logic 1 areinput, and a multiplexer for selecting one of these input lines. Theinput variant selection circuit 18 is provided with the threeconfiguration information input circuits 6. The one bit logic circuitconfiguration information is output from the respective configurationinformation input circuits 6. The input variant selection circuit 18selects one of the seven input lines on the basis of the logic circuitconfiguration information that is output from the respectiveconfiguration information input circuits 6. The logic value input fromthe selected input line is output to the output line.

The lookup table 19 selects and outputs one of 16 bit selected signalson the basis of the four bit selection signal input from the four inputvariant selection circuits 18. The lookup table 19 includes 16configuration information input circuits 6 and a multiplexer 19 a forselecting one of outputs of the respective configuration informationinput circuits 6. The 16 configuration information input circuits 6respectively output selected signals. The multiplexer 19 a performs theselection on the selected signals on the basis of the four bit selectionsignal that is input from the input variant selection circuit 18.

The DFF 20 temporally holds the output value of the lookup table 19. Theoutput value of the lookup table 19 is input to an input terminal D ofthe DFF 20. At the initial rise of a clock CLK that is input from theclock terminal, the DFF 20 takes in and stores the output value of thelookup table 19. The DFF 20 outputs the held logic value from the outputterminal Q. Then, the reverse value is output from the output terminalnQ.

The output variant selection circuit 21 is composed of a 3-input and1-output multiplexer. Two of the input terminals of the output variantselection circuit 21 are connected to the output terminals Q and nQ ofthe DFF 20. The remaining one input terminal of the output variantselection circuit 21 bypasses the DFF 20 and is directly connected tothe output terminal of the lookup table 19. The output variant selectioncircuit 21 incorporates the two configuration information input circuits6. Then, on the basis of the two bit logic circuit configurationinformation that is output from the two configuration information inputcircuits 6, the output variant selection circuit 21 selects one of theinputs from the three input terminals and outputs the input to theoutput terminal.

The output value of the clear signal selection circuit 23 is input tothe clear terminal CLR of the DFF 20. The clear signal selection circuit23 is composed of 4-input and 1-output multiplexer. Two of the inputterminals of the clear signal selection circuit 23 are connected todifferent connection wirings 17. The logic 0 and the logic 1 are inputto the remaining two of the input terminals of the clear signalselection circuit 23. The clear signal selection circuit 23 incorporatesthe two configuration information input circuits 6. Then, on the basisof the two logic circuit configuration information that is output fromthe two configuration information input circuits 6, the clear signalselection circuit 23 selects one input from the four input terminals andoutput the input to the output terminal.

The eight output wiring selection circuit 22 is provided with aplurality of tristate buffers (tri-state buffer) 22 a corresponding tothe connection wirings 17 on one on one basis. In addition, theconfiguration information input circuits 6 are provided corresponding tothe tristate buffers 22 a on one on one basis. The outputs from therespective configuration information input circuits 6 are input tocorresponding strobe input terminals of the tristate buffers 22 a. Theoutput variant of the output variant selection circuit 21 is output tothe data input terminals of the respective tristate buffers 22 a. Thedata output terminals of the respective tristate buffers 22 a areconnected to the corresponding connection wirings 17.

FIG. 4 is a diagram of a configuration example of the switching matrix16 in FIG. 2. The switching matrices 16 are provided at intersections ofthe connection wirings 17. At the intersections of the connectionwirings 17, connection switching circuits 16 a including six analogswitches 16 b are provided. As a result, the four connection wirings 17connected to the connection switching circuit 16 a are divided intogroups with arbitrary two wirings, and the connection wirings 17 in thesame group can be connected to each other.

The configuration information input circuits 6 are providedcorresponding to the respective analog switches 16 b on one on onebasis. In response to the outputs from the respective configurationinformation input circuits 6, turning on/off of the corresponding analogswitches 16 b is performed.

As described above, in this embodiment, the respective logic blocks 15and the respective switching matrices 16 connected by the connectionwirings 17 form the logic configuration variable circuits 7. Then, byinputting the optical signal to the configuration information inputcircuits 6 incorporated in these circuits, the logic configuration ofthe logic configuration variable circuit 7 can be changed.

FIG. 5 is a circuit diagram of a configuration example of theconfiguration information input circuit 6.

The configuration information input circuit 6 in FIG. 5( a) is providedwith the photo diode P, a preset switching element M, and the logicoutput circuit DIG. In this embodiment, a PN photo diode is used for thephoto diode P. The photo diode P is subjected to reverse directionconnection. An anode of the photo diode P is grounded, and a cathodethereof is connected to a power supply via the preset switching elementM. When no light is irradiated, the photo diode P functions as the inputcapacitor C formed of the junction capacitance and the floatingcapacitance.

The preset switching element M is a normal PMOS transistor. The presetsignal nPRESET from the preset control section 11 is input to a gate ofthe preset switching element M. The nPRESET is a negative logic. Whenthe nPRESET is 0, the cathode of the photo diode P is applied with powersupply voltage (the preset voltage) Vc. If no light is irradiated, inthe case of application of the power source voltage Vc, the inputcapacitor C of the photo diode P is charged. When the nPRESET is 1, thecathode of the photo diode P and the power supply are separated fromeach other.

The logic output circuit DIG is a circuit for comparing the cathodevoltage of the photo diode P (that is, the inter-terminal voltage of thephoto diode P) with a predetermined threshold and outputting the voltageafter converted into binary data. The threshold voltage is usually setto about half of the power source voltage Vc. In the example of FIG. 5(a), a normal inverter circuit is used for the logic output circuit DIG.The output of the logic output circuit DIG is output to the respectiveparts in the logic configuration variable circuit 7 as the circuitconfiguration signal CONFIG.

The operation of this circuit will be briefly described with referenceto FIG. 6. FIG. 6 (a) is for the case in which after the preset, theoptical signal is input to the configuration information input circuit 6and FIG. 6 (b) is for the case in which after the preset, no opticalsignal is input to the configuration information input circuit 6.

When the preset signal nPRESET is asserted at a time t₁, the presetswitching element M is turned on. Along with this, the photo diode P issubjected to the reverse bias, and the junction capacitance becomeslarger due to the enlargement of the depletion layer. Then, the inputcapacitor C is charged through the preset switching element M, an anodevoltage Vout of the photo diode P is set to the power source voltage Vc.At this time, a circuit configuration signal CONFIG that is output fromthe logic output circuit DIG is preset to 0. Then, at a time t₂, thepreset signal nPRESET is negated, and the cathode of the photo diode Pand the power supply are separated from each other.

Next, in FIG. 6 (a), from a time t₄ to a time t₅, the optical signal isinput to the configuration information input circuit 6. As a result, acurrent flows from the cathode of the photo diode P to the cathode andthe input capacitor C performs the discharge. Then, in the end, thecathode voltage Vout of the photo diode P is set to the groundpotential. At this time, the circuit configuration signal CONFIG that isoutput from the logic output circuit DIG becomes 1. Even after the inputof the optical signal is completed, the circuit configuration signalCONFIG is kept at 1.

In FIG. 6 (b), even after the preset signal nPRESET is negated, nooptical signal is not input to the configuration information inputcircuit 6. In this case, the input capacitor C keeps the state of beingcharged, and the circuit configuration signal CONFIG is maintained at 0.The input capacitor C gradually discharges while taking several tensmilliseconds due to the leak current, and the cathode voltage Vout ofthe photo diode P gradually decreases from the power source voltage Vc.However, during a period in which the cathode voltage Vout of the photodiode P is higher than the logic threshold voltage of the logic outputcircuit DIG, the circuit configuration signal CONFIG is kept at 0.

In this way, the logic circuit configuration information input throughthe optical signal is kept at the input capacitor C of the photo diodeP.

According to the configuration information input circuit 6 in FIG. 5(b), the preset switching element M and the photo diode P are switched inpositions in the configuration information input circuit 6 in FIG. 5(a). With such a circuit, similarly to the case in FIG. 5( a), the logiccircuit configuration information that is input with use of the opticalsignal is held at the input capacitor C of the photo diode P and can beoutput as the circuit configuration signal CONFIG.

It should be noted that with the circuit in FIG. 5( b), in the casewhere the optical signal is input to the configuration information inputcircuit 6, the circuit configuration signal CONFIG is set to 0, and inthe case where no optical signal is input, the circuit configurationsignal CONFIG is set to 1.

FIG. 7 is a diagram of a configuration example of the output holdingcircuit 10. The output holding circuit 10 is provided with one DFF 25with respect to each of output lines OUT of the logic configurationvariable circuit 7. At the initial rise of the clock CLOCK, the DFF 25takes in and holds the output value OUT of the logic configurationvariable circuit 7. The DFF 25 outputs the held output value to theinput/output circuit 9. The output holding circuit 10 is provided forpreventing such a situation that the output of the logic configurationvariable circuit 7 becomes undetermined while the reconfiguration isconducted on, the logic structure of the internal circuit.

Operations of the optically reconfigurable logic circuit configured asdescribed above will be described below.

First of all, the logic structure of the internal circuit of the logicconfiguration variable circuit 7 is configured. Firstly, the presetcontrol section 11 asserts the preset signal nPRESET for a predeterminedperiod, the input capacitor C of the photo diode P of the respectiveconfiguration information input circuits 6 is charged. When the chargingis completed, the irradiation light control section 12 controls thelight irradiation section 5 so that the light irradiation section 5irradiates the optical memory 4 with the reference light at a desiredangle. As a result, the logic circuit configuration information recordedin the optical memory 4 is taken out as the optical signal. This opticalsignal is input to the photo diode P of the respective configurationinformation input circuits 6. The photo diode P irradiated with thelight discharges the electric charge which has been charged at the inputcapacitor C of the photo diode P as described above. The photo diode Pirradiated with no light holds the electric charge which has beencharged at the input capacitor C of the photo diode P. The operation ofthe reconfiguration on such a logic structure of the internal circuit ofthe logic configuration variable circuit 7 is referred to as “refreshoperation”. The refresh operation is immediately completed within oneclock period.

Then, when the logic configuration variable circuit 7 completes theabove-mentioned refresh operation, the logic circuit executes the logicarithmetic processing.

On the other hand, at the photo diode P irradiated with no light, theelectric charge that has been charged at the input capacitor C of thephoto diode P is gradually discharged due to the leak current. Then, apredetermined period of time elapses, the voltage between the terminalsof the photo diode P becomes equal to or lower than the logic thresholdof the logic output circuit DIG, and the logic circuit configurationinformation is lost. However, during a period in which the logic circuitconfiguration information is lost due to the leak current, the state ofthe logic configuration variable circuit 7 is maintained.

Before the logic circuit configuration information is lost due to theleak current, the above-mentioned refresh operation is executed again,thereby performing the reconfiguration on the logic structure of theinternal circuit of the logic configuration variable circuit 7. In thisway, the logic structure of the internal circuit of the logicconfiguration variable circuit 7 is dynamically reconfigured, wherebythe logic configuration variable circuit 7 is maintained at a desiredlogic structure all the time.

It should be noted that when no logic circuit shuffle occurs while theelectric charge is kept at the input capacitor C of the photo diode P,before the electric charge at the input capacitor C is completelydischarged, the refresh operation needs to be performed with use of theidentical logic circuit configuration information. However, the intervalbetween the refresh operations is a relatively long time of several tensof milliseconds in general. For that reason, the case of performing therefresh operation with used of the identical logic circuit configurationinformation is rare, and it is needless to mention that such a refreshoperation does not disturb the use of the optically reconfigurable logiccircuit 1.

In this way, for holding the logic circuit configuration information atthe configuration information input circuits 6, while the inputcapacitor C of the photo diode P is use and the refresh operation isdynamically and repeatedly used without using any specifically designedmemory element, the mount area of the configuration information inputcircuits 6 can be significantly reduced as compared with the prior artwithout disturbing the operations of the optically reconfigurable logiccircuit 1.

Example 1

As an example, a VLSI chip of the optically reconfigurable logic circuit1 is designed with use of a CMOS standard process of 0.35 μm as shown in(Table 1). A core voltage and an I/O cell voltage are unified to 3.3 V.A cell size of the photo diode P is set to 25.5 μm×25.5 μm, and a cellsize including the preset switching element M and the logic outputcircuit DIG is set to 40.5×33.0 μm. A pn photo diode is used for thephoto diode P and composed between an N well and a P substrate. Photodiode cells are located every 99 μm on two-dimension. The total numberof the photo diodes P is set to 605. Under such conditions, theoptically reconfigurable logic circuit 1 is designed. While the mountarea of the conventional ODRGA reconfiguration circuit is 618.75 μm²,the mount area of the reconfiguration circuit according to thisembodiment can be reduced to 74.25 μm².

(End of the Example)

TABLE 1 Technology 0.35 μm double-poly triple-metal CMOS process Chipsize   4.9 × 4.9 [mm] Supply Voltage Core 3.3 V, I/O 3.3 V Photodiodesize 25.5 × 25.5 [μm] Interval between h = 99 v = 99 [μm] PhotodiodesNumber of 605 Photodiodes Number of 4 Logic Blocks Number of 5 SwitchingMatrices Number of 16 I/O bits

The mount area I of the reconfiguration circuit is defined by(Expression 1).

I=(P+R)×N  [Expression 1]

Herein, reference symbol P denotes the mount area of the photo diodesand reference symbol R denotes a mount area of other circuit partsincluding a flip-flop, a latch, an inverter, and other transistors.Reference symbol N denotes the number of programming elements. In theabove-mentioned design of (Example 1), the photo diode P is designed tohave a large size for facilitating the aligning between the VLSI section3 and the optical section 2. However, if the aligning accuracy isincreased, it is considerable that this size may be smaller than 25 μm².At that time, as a relation P<<R is established, it is extremelyimportant to decrease R for reducing the mount area I.

The optically reconfigurable logic circuit 1 according to thisembodiment reduces the mount area to ⅛ or smaller as compared with theconventional circuit. This size is significantly effective forincreasing the gate density.

Finally, the operations of the output holding circuit 10 will bedescribed collaterally. FIG. 8 is a timing chart for a relation betweenthe respective blocks and the output value of the output holding circuit10 before and after the refresh operation of the logic configurationvariable circuit 7. In FIG. 8, a reconfiguration clock represents aclock to be input to the preset control section 11, the irradiationlight control section 12, and the timer 13. Herein, the identical clockCLOCK is used for the clock input to the output holding circuit 10 andthe reconfiguration clock.

During one clock period from the time t₁ to the time t₂, theabove-mentioned refresh operation is conducted, whereby the logicconfiguration variable circuit 7 is reconfigured from a circuit A to acircuit B. As a result, during the period from the time t₁ to the timet₂, the output value OUT of the logic configuration variable circuit 7temporarily becomes undetermined. On the other hand, the output holdingcircuit 10 takes in and holds the output value OUT of the logicconfiguration variable circuit 7 at the initial rise of the clock CLOCKand outputs it to the input/output circuit 9. Therefore, at the initialrise of the clock CLOCK at the time t₁, the output holding circuit 10keeps outputting the value while the output value of the circuit A iskept by the time t₂. Then, at the initial rise of the clock CLOCK at thetime t₂, the output holding circuit 10 holds the output value of thecircuit B and outputs it. As a result, during the period from the timet₁ to the time t₂, such a situation is prevented that the output valueof the optically reconfigurable logic circuit 1 becomes undetermined.

It should be noted that FIG. 7 shows the example in which the DFF 25 isused for the output holding circuit 10, but a configuration including atransmission gate 26 and a latch 27 shown in FIG. 9 may be used for theconfiguration of the output holding circuit 10.

As described above, in the optically reconfigurable logic circuit 1according to this embodiment, an unnecessary memory function of the VLSIsection having the conventional ORGA or ODRGA is eliminated. In otherwords, in the conventional ORGA or ODRGA, the memory function (the“memory function” herein is a function for constantly holdinginformation and is not a function for temporarily holding information)is present in both the optical section and the VLSI section. In theoptically reconfigurable logic circuit 1 according to this embodiment,the redundant memory function of the VLSI section is eliminated. Then,such a method is adopted for temporarily holding the logic circuitconfiguration information that is input from the optical section withuse of the junction capacitance and the floating capacitance of thephoto diode. In a shorter interval than a time period in which the heldlogic circuit configuration information disappears due to the leakcurrent, the refresh operation is repeatedly performed on the junctioncapacitance and the floating capacitance of the photo diode, whereby theoptical section is caused to maintain the logic circuit configuration ofthe VLSI section by sequentially transferring the held logic circuitconfiguration information to the VLSI section. With the adoption of sucha dynamic method, the redundant memory function is removed and it ispossible to significantly decrease the mount area of the VLSI section.

Second Embodiment

FIG. 10 is a block diagram of an entire function configuration of anoptically reconfigurable logic circuit according to a second embodimentof the present invention. the optically reconfigurable logic circuit 1′according to this embodiment is basically the same as the opticallyreconfigurable logic circuit 1 shown in FIG. 1, but in the VLSI section3, but is provided with two of the logic configuration variable circuits7 a and 7 b having the same configuration and includes an output circuit30 composed of an open collector circuit instead of the output holdingcircuit 10. In addition, the light irradiation section 5 canindependently input optical signals to the respective logicconfiguration variable circuits 7 a and 7 b. Furthermore, theirradiation light control section 12 also functions as reconfigurationcontrol means for controlling the logic reconfiguration while performinga switch so that at the same point in time, one of the logicconfiguration variable circuits 7 a and 7 b is only irradiated with theoptical signal.

FIG. 11 is a diagram of a configuration of the output circuit 30. Thelogic configuration variable circuits 7 a and 7 b are connected inparallel so as to have a common input/output line for the logic variant.The output circuit 30 is provided with an open collector circuit 31 withrespect to respective output lines of the logic circuits 7 a and 7 b.

The identical logic circuit configuration information is input to thelogic configuration variable circuits 7 a and 7 b, thereby structuringthe identical logic configuration.

In such a configuration, when the refresh operation is performed, firstof all, the irradiation light control section 12 performs such a controlthat the optical signal is input to the logic configuration variablecircuit 7 a with use of the optical section 2. At this time, no opticalsignal is input to the logic configuration variable circuit 7 b, andthus the original logic configuration is kept. Therefore, while thelogic circuit of the logic configuration variable circuit 7 a isconfigured, the output value of the optically reconfigurable logiccircuit 1′ is guaranteed by the logic configuration variable circuit 7b.

When the reconfiguration on the logic configuration variable circuit 7 ais completed, subsequently, the irradiation light control section 12inputs the optical signal of the identical logic circuit configurationinformation to the logic configuration variable circuit 7 b with use ofthe optical section 2 and performs such a control that thereconfiguration on the logic circuit of the logic configuration variablecircuit 7 b is conducted. At this time, no optical signal is input tothe logic configuration variable circuit 7 a, and accordingly the newlystructured logic configuration is kept. Therefore, while the logiccircuit of the logic configuration variable circuit 7 b is structured,the output value of the optically reconfigurable logic circuit 1′ isguaranteed by the logic configuration variable circuit 7 a.

In this way, according to this embodiment, the open collector circuits31 are provided at the output stages of the logic configuration variablecircuits 7 a and 7 b, and when the refresh operation is performed, whileone of the configurations of the logic configuration variable circuitsis kept, the other logic circuit reconfiguration is performed, wherebyit is possible to prevent such a situation that during the refreshoperation of the logic circuit, the output value of the opticallyreconfigurable logic circuit 1′ becomes undetermined.

It should be noted that in this embodiment, the two logic configurationvariable circuits 7 a and 7 b are used to perform the switching on therefresh operation, but three or more logic configuration variablecircuits may be used to perform the switching on the refresh operation.

Third Embodiment

FIG. 12 is a block diagram of an entire function configuration of anoptically reconfigurable logic circuit 1 according to a thirdembodiment. The optically reconfigurable logic circuit 1 according tothis embodiment has different points from the optically reconfigurablelogic circuit 1 according to the first embodiment (refer to FIG. 1) inthat the output holding circuit 10 is omitted, the logic configurationvariable circuit 7 is replaced by the logic configuration variablecircuit 7′, and a pass transistor control section 40 is newly added, andother configurations are identical. The logic configuration variablecircuit 7′ has the same configurations described in FIGS. 2 to 4 but isdifferent from the first embodiment in terms of the structure of theconfiguration information input circuit 6 (FIG. 5).

The difference between the structure of the configuration informationinput circuit 6 according to the first embodiment and that of theconfiguration information input circuit 6 according to the thirdembodiment is shown in FIG. 13.

FIG. 13( a) shows the configuration information input circuit 6 in FIG.5( a) at a transistor level. Reference numerals in the respectivecircuit elements correspond to FIG. 5( a). In FIG. 13( a), the left-handside of a dashed-dotted line in the center represents the configurationinformation input circuit 6 and the right-hand side of the dashed-dottedline represents the logic configuration variable circuit 7 (gate arraycircuit). In FIG. 13( a), only an input buffer 41 is shown and otherparts are omitted with regard to the logic configuration variablecircuit 7. In this way, the logic output circuit DIG is structured by anormal inverter circuit composed of two PMOSs.

As described above, in this circuit, the configuration information ofthe logic configuration variable circuit 7 is stored in the inputcapacitor C that is the junction capacitance of the photo diode P. Theminimum configuration elements of the configuration information inputcircuit 6 in FIG. 13( a) are only the photo diode P and the presetswitching element M (the logic output circuit DIG may be added asnecessary), and therefore there is a merit of easily fabricating theoptically reconfigurable logic circuit of the high gate number.

The reconfiguration procedure for the optically reconfigurable logiccircuit 1 according to the first embodiment using the configurationinformation input circuit in FIG. 13( a) is as follows. First of all,the preset signal nPRESET is asserted for a given time by the presetcontrol section 11, thereby achieving continuity of the preset switchingelement M. As a result, the programming state of the logic configurationvariable circuit 7 is cleared once. After the junction capacitance ofthe photo diode P (that is, the input capacitor C) is fully charged, theoptical signal is irradiated and input from the optical section 2. As aresult, the circuit configuration information is written to therespective photo diodes P, and the information is held at the inputcapacitor C.

While this reconfiguration procedure is executed, the logicconfiguration variable circuit 7 cannot operate as the logic circuit isin the undetermined state, and the execution of the logic configurationvariable circuit 7 is not performed until the reconfiguration procedureis completed. FIG. 14 is a timing chart for a timing of thereconfiguration operation of the optically reconfigurable logic circuit1 according to the first embodiment and the execution of the logicconfiguration variable circuit 1. As shown in FIG. 14, the logic circuitreconfiguration operation and the execution of the logic configurationvariable circuit 7 are not performed in parallel. In the case of anapplication in which the optically reconfigurable logic circuit 1 isdynamically reconfigured, this overhead is too long to ignore.

Whereas FIG. 13( b) shows the configuration information input circuit 6according to the third embodiment at a transistor level. In FIG. 13( b)as well, the left-hand side of a dashed-dotted line in the centerrepresents the configuration information input circuit 6 and theright-hand side of the dashed-dotted line in the center represents thelogic configuration variable circuit 7 (gate array circuit). Also, withregard to the logic configuration variable circuit 7, only the inputbuffer 41 is shown and other parts are omitted. When FIG. 13( b) iscompared with FIG. 13( a), the configuration information input circuit 6according to this embodiment is characterized in that a pass transistorM2 is newly provided at the output stage of the logic output circuitDIG. The pass transistor M2 performs continuity/interruption of acircuit configuration signal transmission line 42 for outputting thecircuit configuration signal from the configuration information inputcircuit 6 to the logic configuration variable circuit 7. A configurationenable signal (Configuration Enable signal) CE that is output from thepass transistor control section 40 is input to a gate terminal of thepass transistor M2. As a result, the interruption/continuity of the passtransistor control section 40 is controlled by the pass transistorcontrol section 40.

The configuration information input circuit 6 according to the thirdembodiment shown in FIG. 13( b) while the circuit configuration signalof the input capacitor C is updated, the previous circuit configurationsignal is held at a parasitic capacitance (hereinafter referred to as“output capacitor C′”) of the circuit configuration signal transmissionline 42 or an input state of the logic configuration variable circuit 7to which the circuit configuration signal transmission line 42 isconnected. The input stage of the logic configuration variable circuit 7is usually structured by an inverter gate, a NAND gate, a transmissiongate, and the like, and the output capacitor C′ of the input stage hassufficient capacitance with which the previous circuit configurationsignal is held while the circuit configuration signal of the inputcapacitor C is updated. Therefore, after the pass transistor M2 isinterrupted, the circuit configuration signal is held at the outputcapacitor C′, and even while the circuit configuration signal of theinput capacitor C is updated, the logic configuration of the logicconfiguration variable circuit 7 can be maintained.

FIG. 15 is a timing chart for a timing in which the reconfigurationoperation on the optically reconfigurable logic circuit 1 according tothe third embodiment and the execution of the logic configurationvariable circuit 7. After the optical signal for the programming of thelogic configuration variable circuit 7 is input, the configurationenable signal CE is asserted for a given time, and thus the circuitconfiguration signal is input to the logic configuration variablecircuit 7 and the output capacitor C′. The pulse width in which theconfiguration enable signal CE is asserted is set longer at least than aperiod of the logic reconfiguration on the logic configuration variablecircuit 7. As a result, the reconfiguration interval is a sum of thepulse width of the preset nPRESET, the irradiation period of the opticalsignal, and the pulse width of the configuration enable signal CE. Whilethe enable signal CE is negated, even in the irradiation period of theoptical signal, the circuit configuration information is held at theoutput capacitor C′. The execution of the logic configuration variablecircuit 7 and the reconfiguration operation of the opticallyreconfigurable logic circuit 1 can be performed in parallel, whereby itis possible to accelerate the dynamic reconfiguration and the executionof the gate array.

Furthermore, as shown in FIG. 16, a circuit for performing partialreconfiguration can be easily structured. In FIG. 16, the logic outputcircuit with the pass transistor 43 is shown by integrating the logicoutput circuit DIG and the pass transistor M2 in FIG. 13( b). Thedynamic optical reconfiguration array has a plurality of configurationinformation input circuits 6 b connected in parallel with respect to oneoptical reconfiguration instruction circuit 6 a. The opticalreconfiguration instruction circuits 6 a and 6 b have the sameconfiguration as that shown in FIG. 13( b). To the preset switchingelements M of the respective optical reconfiguration instructioncircuits 6 a, the preset signal nPRESET from the preset control section11 is input. Then, an output of a logic output circuit with passtransistor 43 of the optical reconfiguration instruction circuit 6 a isinput to the preset switching element M of the respective configurationinformation input circuits 6 b. Furthermore, the output of the logicoutput circuit with the pass transistor 43 of the respectiveconfiguration information input circuits 6 b is input to the logicconfiguration variable circuit 7 as the circuit configuration signal.

FIG. 17 shows a schedule for the dynamic reconfiguration on the dynamicoptical reconfiguration array for performing the partial reconfigurationand the execution of the logic configuration variable circuit 7. Therespective logic blocks 15, the respective switching matrices 16, andthe I/O blocks 14 in FIG. 2 are provided with the opticalreconfiguration instruction circuits 6 a. The preset signal nPRESET ofthe respective configuration information input circuits 6 b in each ofthe blocks is driven by the optical reconfiguration instruction circuit6 a of the corresponding block. First of all, an optical signal is inputto the optical reconfiguration instruction circuit 6 a of the block thatshould be reconfigured first. Next, the circuit of the block thatincludes the optical reconfiguration instruction circuit 6 a irradiatedwith the optical signal is reconfigured. Finally, execution of thereconfigured gate array circuit is performed. In this way, the operationfor each block can be performed in a pipe line manner as shown in FIG.17.

INDUSTRIAL APPLICABILITY

The present invention is useful as the programmable logic circuit thatcan optically rewrite the logic configuration in various electricappliance industries.

1. An optically reconfigurable logic circuit, comprising: aconfiguration information input circuit that includes a photoconductivedevice for causing continuity/interruption in response to lightirradiation input, and converts and outputs an optical signal thatcontains logic circuit configuration information with use of thephotoconductive device into an electric circuit configuration signal;and a logic configuration variable circuit for performing logicconfiguration of an internal circuit on the basis of the circuitconfiguration signal, the optically reconfigurable logic circuit beingcharacterized in that a control is performed in such a manner that thelogic circuit configuration information input from the optical signal isheld at a parasitic capacitance (hereinafter referred to as “inputcapacitor”) between the terminals of the photoconductive device in anon-continuity state as the circuit configuration signal, and as theinput capacitor is preset and a next optical signal is input before theheld circuit configuration signal disappears due to leak discharge, thelogic circuit configuration information is dynamically held at the inputcapacitor.
 2. The optically reconfigurable logic circuit according toclaim 1, characterized in that the photoconductive device is a photodiode subjected to reverse bias connection.
 3. The opticallyreconfigurable logic circuit according to claim 1, characterized in thatthe configuration information input circuit comprises a logic outputcircuit for quantizing an inter-terminal voltage of the photoconductivedevice and outputting the resultant as a logic output value, and thelogic output circuit quantizes an electric signal which is output whenthe photoconductive device converts the optical signal, and outputs theresultant as the circuit configuration signal.
 4. The opticallyreconfigurable logic circuit according to claim 1, further comprising:preset control means for performing a preset control for charging theinput capacitor by applying the photoconductive device with a presetvoltage in a reverse bias direction; irradiation light control means forperforming irradiation control for writing logic circuit configurationinformation to the configuration information input circuit by settingthe optical signal in an on state in a predetermined period of time andcausing continuity of the irradiated photoconductive device on the basisof the optical signal after the input capacitor is charged through thepreset control; and timing generation means for outputting a presettiming signal to the preset control means with a predetermined delaytime after the logic circuit configuration information is written to theconfiguration information input circuit through the irradiation lightcontrol, the optically reconfigurable logic circuit characterized inthat the preset control means executes the preset control when thepreset timing signal is input.
 5. The optically reconfigurable logiccircuit according to claim 4, characterized in that the timinggeneration means outputs a preset timing signal to the preset controlmeans with a delay time shorter than a period in which theinter-terminal voltage of the photoconductive device that is previouslyset to the preset voltage through the preset control falls to be equalor lower than a predetermined logic threshold due to the leak discharge.6. The optically reconfigurable logic circuit according to claim 4,characterized in that the configuration information input circuitincludes a preset switching element for performing turning on/off of thepreset voltage applied between electrodes of the photoconductive device,and the preset control means asserts in a predetermined period thepreset signal for turning on the preset switching element.
 7. Theoptically reconfigurable logic circuit according to claim 4, furthercomprising logic output holding means for holding a logic output valueof the logic configuration variable circuit at a timing before a timepoint when the inter-terminal voltage of the photoconductive devicefalls to be equal to or lower than the predetermined logic threshold asthe input capacitor charged to the preset voltage through the presetcontrol involves leak discharge.
 8. The optically reconfigurable logiccircuit according to claim 7, characterized in that the configurationinformation input circuit includes a preset switching element forperforming turning on/off of a preset voltage that is applied betweenthe electrodes of the photoconductive device, the preset control meansasserts in a predetermined period the preset signal for turning on thepreset switching element, and the logic output holding means holds thelogic output value of the logic configuration variable circuit at atiming before the preset control means asserts the preset signal.
 9. Theoptically reconfigurable logic circuit according to claim 4,characterized by further comprising: a pass transistor for causingcontinuity/interruption of a circuit configuration signal transmissionline for inputting the circuit configuration signal, which is outputfrom the configuration information input circuit, to the logicconfiguration variable circuit; and pass transistor control means forperforming such a control that the circuit configuration signal is heldat one of the circuit configuration signal transmission line and aparasitic capacitance (hereinafter referred to as “output capacitor”) ofan input circuit of the logic configuration variable circuit to whichthe circuit configuration signal transmission line is connected as thepass transistor is set in the interruption state during the irradiationof the optical signal.
 10. The optically reconfigurable logic circuitaccording to claim 8, characterized in that the pass transistor controlmeans performs such a control that, after irradiation of the opticalsignal, as the input capacitor charged to the preset voltage through thepreset control involves leak discharge, before a time point when theinter-terminal voltage of the photoconductive device falls to be equalor lower than the predetermined logic threshold, at least during aperiod in which logic reconfiguration on the logic configurationvariable circuit is completed, the pass transistor is set in thecontinuity state, and during the irradiation of the optical signal, thepass transistor is set in the interrupted state.
 11. The opticallyreconfigurable logic circuit according to claim 4, further comprisingoptical signal input means for irradiating the configuration informationinput circuit that contains the logic circuit configuration information,the optically reconfigurable logic circuit being characterized in thatthe irradiation light control means controls turning on/off of selectionand irradiation of the optical signal output from the optical signalinput means.
 12. The optically reconfigurable logic circuit according toclaim 11, characterized in that at least two of the logic configurationvariable circuits are connected in parallel to each other with a commoninput/output terminal for a logic variable, the optical signal inputmeans can independently input an optical signal that contains the logiccircuit configuration information to the configuration information inputcircuits corresponding to the respective logic configuration variablecircuit, and the optical signal input means includes open collectorcircuits provided at output stages of the logic configuration variablecircuits and reconfiguration control means for performing such a controlon the optical signal input means that switching is performed among thelogic configuration variable circuits connected in parallel to eachother so that at the same time point, the configuration informationinput circuit corresponding to at least one of the logic configurationvariable circuits is not irradiated with the optical signal and opticalsignals that contain the same logic circuit configuration informationare input to the logic configuration variable circuits.
 13. Theoptically reconfigurable logic circuit according to claim 2,characterized in that the configuration information input circuitcomprises a logic output circuit for quantizing an inter-terminalvoltage of the photoconductive device and outputting the resultant as alogic output value, and the logic output circuit quantizes an electricsignal which is output when the photoconductive device converts theoptical signal, and outputs the resultant as the circuit configurationsignal.
 14. The optically reconfigurable logic circuit according toclaim 2, further comprising: preset control means for performing apreset control for charging the input capacitor by applying thephotoconductive device with a preset voltage in a reverse biasdirection; irradiation light control means for performing irradiationcontrol for writing logic circuit configuration information to theconfiguration information input circuit by setting the optical signal inan on state in a predetermined period of time and causing continuity ofthe irradiated photoconductive device on the basis of the optical signalafter the input capacitor is charged through the preset control; andtiming generation means for outputting a preset timing signal to thepreset control means with a predetermined delay time after the logiccircuit configuration information is written to the configurationinformation input circuit through the irradiation light control, theoptically reconfigurable logic circuit characterized in that the presetcontrol means executes the preset control when the preset timing signalis input.
 15. The optically reconfigurable logic circuit according toclaim 3, further comprising: preset control means for performing apreset control for charging the input capacitor by applying thephotoconductive device with a preset voltage in a reverse biasdirection; irradiation light control means for performing irradiationcontrol for writing logic circuit configuration information to theconfiguration information input circuit by setting the optical signal inan on state in a predetermined period of time and causing continuity ofthe irradiated photoconductive device on the basis of the optical signalafter the input capacitor is charged through the preset control; andtiming generation means for outputting a preset timing signal to thepreset control means with a predetermined delay time after the logiccircuit configuration information is written to the configurationinformation input circuit through the irradiation light control, theoptically reconfigurable logic circuit characterized in that the presetcontrol means executes the preset control when the preset timing signalis input.
 16. The optically reconfigurable logic circuit according toclaim 5, characterized in that the configuration information inputcircuit includes a preset switching element for performing turningon/off of the preset voltage applied between electrodes of thephotoconductive device, and the preset control means asserts in apredetermined period the preset signal for turning on the presetswitching element.
 17. The optically reconfigurable logic circuitaccording to claim 5, further comprising logic output holding means forholding a logic output value of the logic configuration variable circuitat a timing before a time point when the inter-terminal voltage of thephotoconductive device falls to be equal to or lower than thepredetermined logic threshold as the input capacitor charged to thepreset voltage through the preset control involves leak discharge. 18.The optically reconfigurable logic circuit according to claim 5,characterized by further comprising: a pass transistor for causingcontinuity/interruption of a circuit configuration signal transmissionline for inputting the circuit configuration signal, which is outputfrom the configuration information input circuit, to the logicconfiguration variable circuit; and pass transistor control means forperforming such a control that the circuit configuration signal is heldat one of the circuit configuration signal transmission line and aparasitic capacitance (hereinafter referred to as “output capacitor”) ofan input circuit of the logic configuration variable circuit to whichthe circuit configuration signal transmission line is connected as thepass transistor is set in the interruption state during the irradiationof the optical signal.
 19. The optically reconfigurable logic circuitaccording to claim 5, further comprising optical signal input means forirradiating the configuration information input circuit that containsthe logic circuit configuration information, the opticallyreconfigurable logic circuit being characterized in that the irradiationlight control means controls turning on/off of selection and irradiationof the optical signal output from the optical signal input means. 20.The optically reconfigurable logic circuit according to claim 6, furthercomprising optical signal input means for irradiating the configurationinformation input circuit that contains the logic circuit configurationinformation, the optically reconfigurable logic circuit beingcharacterized in that the irradiation light control means controlsturning on/off of selection and irradiation of the optical signal outputfrom the optical signal input means.